A High-Level Synthesis Scheduling and Binding ..

This project focusses on a template defined in VHDL that allows for a simulated annealing only C-to-FPGA compiler to map software code onto this parameterized template via an architecture space exploration algorithm. Specifically the algorithm invokes a pipeline latency balancing routine, with foot-print cost managed by a pair of scheduling and binding algorithms that are cognizant of the diversity in device primitives in FPGAs (LUT, FF, DSP48, BRAM). This project is motivated by the need for high speed low power schedulers needed in autonomous realtime systems and a simple way of harnessing the power of FPGAs to support such accelerators.

Knight, 'Scheduling and Binding Algorithms for High-Level Synthesis,' Proc.

AB - In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.


Improved Algorithms for High-Level Synthesis and …

AI-Hashimi, 'Simultaneous Scheduling, Allocation and Binding in High-level Synthesis,' Electronics Letters, vol.

N2 - In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.


Course Listing - Farmingdale State College

In this. paper, we propose a high-level synthesis method targeting distributed/shared-register architectures. Our method repeats (1) scheduling/FU binding, (2) register allocation, (3) register binding, and (4) module placement. By feeding back ftoorplan information from (4) to (1), our method obtains a distributed/shared-register architecture where its scheduling/ binding as well as ftoorplaning are simultaneously optimized. Experimental results show that the area is decreased by 13.6% while maintaining the performance of the circuit equal with that using distributed-register architectures.

AET 105 Fuel Systems - SI Engines

With the miniaturization of LSIs and its increasing performance, demand for high-functional portable devices has grown significantly. At the same time, battery lifetime and device overheating are leading to major design problems hampering further LSI integration. On the other hand, the ratio of an interconnection delay to a gate delay has continued to increase as device feature size decreases. We have to estimate interconnection delays and reduce energy consumption even in a high-level synthesis stage. In this paper, we propose a high-level synthesis algorithm for huddle-based distributed-register architectures (HDR architectures) with clock gatings based on concurrency-oriented scheduling/functional unit binding. We assume coarse-grained clock gatings to huddles and we focus on the number of control steps, or , at which we can apply the clock gating to registers in every huddle. We propose two methods to increase gating steps: One is that we try to schedule and bind operations to be performed at the same timing. By adjusting the clock gating timings in a high-level synthesis stage, we expect that we can enhance the effect of clock gatings more than applying clock gatings after logic synthesis. The other is that we try to synthesize huddles such that each of the synthesized huddles includes registers which have similar or the same clock gating timings. At this time, we determine the clock gating timings to minimize all energy consumption including clock tree energy. The experimental results show that our proposed algorithm reduces energy consumption by a maximum of 23.8% compared with several conventional algorithms.

Directory of Modules 2017-18 Queen Mary University of …

Hsu, 'A Formal Approach to the Scheduling Problem in High Level Synthesis,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.