Synplify Premier software provides all of the features of Synplify Pro as well as a comprehensive suite of tools for advanced FPGA design.
- Incremental, block-based and bottom-up flows for consistent results from one run to the next
- Automatic compile points incremental flow for up to 4x faster runtime while maintaining QoR
- Accelerated runtimes with support for up to 4 processors
- Scripting and Tcl/Find support for flow automation and customizable synthesis, debug and reporting
- Optimal area and timing results using FPGAs from Achronix, Altera, Lattice, Microsemi, Xilinx
- Hierarchical team design flow allowing parallel and/or geographically distributed design development
- Comprehensive language support including Verilog, VHDL, SystemVerilog, VHDL-2008 and mixed-language design
- FSM Compiler and FSM Explorer for automatic extraction and optimization of finite state machines from RTL
- Graphical state machine viewer to automatically create bubble diagrams for debugging and documenting FSMs
- Automatic memory and DSP inference provides automatic implementation of a design with optimal area, power and timing quality of results
- Incremental static timing for analysis allows updates to timing exception constraints with immediate visibility into results, without re-synthesis
- HDL Analyst interactive graphical analysis and debug tool for design diagnosis, problem isolation and functional and performance analysis
With its HPM capabilities, Synplify answers that question so that, not only parallel machine processing but, perhaps even more importantly, human parallelism becomes another viable increment toward greater overall efficiency.Cheong Tse is a staff corporate applications engineer for FPGA-based synthesis software tools at Synopsys.
Diamond Version History - Lattice Semiconductor
For high-density, high-performance FPGA designs, the ability to iterate rapidly during design and debugging stages is critical to meet time-to-market demands. Today’s FPGA designers are encountering problems traditionally associated with ASIC designs, especially long place-and-route compilation times and difficulties achieving timing closure. To address these issues, FPGA and EDA vendors are beginning to offer incremental design and compilation capabilities previously available only with ASIC design tools. These capabilities include top-down methodologies that support evolving designs and engineering change orders (ECO), as well as bottom-up design methodologies including team-based design flows. Incremental compilation improves productivity by dramatically reducing design iteration times and preserving results to reach timing closure more easily. This paper presents incremental compilation methodologies using Mentor Graphics ® Precision RTL Synthesis and Altera ® Quartus ® II software, including user scenarios and design recommendations to maximize the benefits and ensure good quality of results in an incremental compilation flow. 2 Incremental Compilation Benefits Conventionally, a hierarchical design is flattened into a single netlist before logic synthesis and fitting (or placement and routing). The entire design is then recompiled every time there is a change in the design. One reason for this behavior is to obtain optimal quality of results. By processing the entire design, the compiler can perform global optimizations to improve area and performance. However, this leads to long placement and routing times, and typically causes major changes in the placement results and the design’s performance even for minor changes in source code or settings. There are many situations in which a more incremental compilation flow is desirable. Incremental compilation allows a design to be organized into logical partitions for synthesis and fitting.